Address selection system for magneticore matrix memory apparatus



1963 TAKASHI ISHIDATE 3,075,181 ADDRESS SELECTION SYSTEM FOR MAGNETIC-CORE MATRIX MEMORY APPARATUS Filed Feb. 11, 1958 2 Sheets-Sheet 1 0 '0 PARAMETIMIVS- Q {1,coswt X C1 24 PRIOR ART 1; cos i; *2! 1/ 429 TISHIDATE Attorney Jan. 22, 1963 TAKASHI ISHIDATE ADDRESS SELECTION SYSTEM FOR MAGNETIC-CORE MATRIX MEMORY APPARATUS 2 Sheets-Sheet 2 Filed Feb. 11, 1958 tI'sWKb'ATE A Home y United States Patent M 3,075,181 ADDRESS SELECTION SYSTEM FQR MAGNETIC- CORE MATRIX MEMORY APPARATUS Talrashi Ishidate, Tokyo, Japan, assignor to Nippon Electric Company Limited, Tokyo, Japan, a corporation oi Japan Filed Feb. 11, 1958, Ser. No. 714,644 Claims priority, application Japan Feb. 22, 1957 4 Claims. (Cl. 349-174) This invention relates to an address selection system for alternating-current two-frequency-type magnetic-core matrix memory apparatus used with circuits containing the switching elements using subharmonic oscillations (sometimes referred to as Parametron).

One of the objects of the invention is to provide a selection system for a magnetic-core matrix memory apparatus operating on alternating current which will require less current to operate than systems of this type heretofore used and in which the characteristic requirements of the individual memory cores will be less rigorous than those of the cores of known systems.

The above-mentioned and other features and objects of this invention and the manner of attaining them will become more apparent and the invention itself will be best understood by reference to the following description of an embodiment of the invention taken in conjunction with the accompanying drawings, in which:

FIGS. 1 and 2 are schematic representations of a conventional system;

FIG. 3 is a schematic representation of the system of the invention; and

FIG. 4 is a family of current curves illustrating the operation of the system of FIG. 3.

FIG. 1 illustrates an example of the conventional system in which an ordered set of sixteen magnetic cores,

such as C11, C12 C44, is arranged in a square array, or a matrix. While the present invention is exemplified by a number of sixteen cores, the invention will equally apply, in general, to cases in which a multiplicity of magnetic cores are arranged in a matrix form.

The switching elements P1 to P4 which are in the circuits of the columns YlY4 are the Parametrons which use subharmonic oscillations for their operation. A Parametron is a resonance element having inductance and capacity one of which, usually the inductance, is varied periodically. A Parametron having a variable inductance may be made of two ferrite cores each having a primary winding of a single turn, these windings being connected in series, and a secondary winding of ten turns, these windings being connected in reverse. The series connected secondary windings are connected across the plates of a condenser. The primary windings are excited by an alternating current and the circuit including the secondary windings and the condenser is tuned to one half of the frequency of the exciting current. When excitation current is applied to the primary windings, the resonance circuit is shocked into oscillation at half the frequency of the excitation current and at either of two phases 180 apart depending on a previous excitation.

The Parametron switching elements are illustrated schematically by a circle with only the input and output connections shown.

To have the system of FIG. I perform the address selection, select any one column out of Y1, Y2, Y3 and Y4 and excite one of the switching elements P1 through P4 by a current I cos 2wt (w=21rf) of the frequency 2f. The element thus selected will supply a current 1, cos wt to the associated Y column. On the other hand, select 3,075,181 Patented Jan. 22, 1963 one of the horizontal row conductors from among X1, X2, X3 and X4 to supply a current I cos it I cos 2 to insure the supply of current necessary for memory to the magnetic core.

FIG. 2 illustrates diagrammatically a publicly known system to be considered an improvement of the system illustrated in FIG. 1. In this figure, P represents a switching element using subharmonic oscillations fed with a current I cos 2W2 from an electric source Z. (It will be noted here that the value of I in FIGS. 2 or 3 by no means coincides with that of 12f in FIG. 1).

This system performs the address selection utilizing operations, as follows: Instead of using one switching element per column, a current of frequency is shared by an X-row and Y-column. In other words, a current 1 I cos 2 2 2 is con-ducted in each one conductor selected from the X and Y axes. As a consequence, a current w I cos t 2 2 will flow through the magnetic core at the intersection while either 0 or 1 I cos 2 2 will flow through the rest of magnetic cores.

It will be known, then that the characteristics of the memory magnetic core must be rigorous enough so that writing-in, reading-out or distracting-of-memory may not be performed by a current 1 wt 1% cos flowing through a non-selected core and that the complete write-in and read-out operations may be performed by a current wt I cos 2 2 coaster Whereas t-wo electric sources of frequency for supplying a current 1 I cos 2 are assigned. Stated inore specifically, two different kinds of currents, one

1 wt 7r I =I c s l S2 2 "i" which is advanced in phase by with respect to an optimum current for writing-in or reading-out, and the other which is delayed in phase by with respect to said optimum current, are assigned to an X-row and a Y-column, so that an optimum current I cos 4 is available at only the selected intersection through which a current I -[-1 flows.

Assume that when a current flows through a magnetic core which has been memorized the read-out output is proportional to the square of said current. Then the current through a non-selected core will be either of the three as follows:

As a consequence, the read-out output will be either of the three, as follows:

where K is a constant.

The result is that the output will have ,a phase difference switching element P, giving no information to said element.

On the other hand, since the read-out output of the selected core is expressed as the output will be in phase with the oscillation in the switching element, thus giving information. Generally speaking, the value of K varies with the current flowing through a magnetic core and the value for a range in which cores are used as a memory apparatus will be small for a small current and viceversa. In other words, the address selection performed is not dependent only on the phasing relations; the amplitude difference between the read-out outputs from the selected and non-selected cores will also assist in ensuring the operation of address selection.

Now, a case of writing-in will be described. Suppose a current from a switching element be expressed as I =iI cos wt, then through a'non 'selected core, either of the three currents as follows will flow:

I :lzI cos wt the information which has been memorized prior to the g with respect to the oscillation phase 1 cos wt of the V write-in operation will not be extracted.

On the other hand,'a current I ;|I +I which is equal [0 i cos glib cos wt will flow through the selected magnetic core, thus enabling new information to be written in. For a clear understanding of these relationships, let an example of various waveforms for a case of be illustrated in FIG. 4.

In FIG. 4, 1 denotes a current of frequency that flows through the selected magnetic core, or I -H which is equal to cos 2 denotes a current of frequency f, or 1 (=0.4 cos wt) supplied from the switching element P; 3 denotes a composite waveform of 1 and 2, or a writein current flowing through the selected magnetic core which is equal to I I+I or cos gt +0.4 cos wt 4 denotes an example of current flowing through a nonselected magnetic core which is equal to 1 cos #5 According to this figure, since the maximum amplitudes of the write-in current 4 through the non-selected magnetic core in the positive and negative directions are equal and they do not exceed those of waveform 1, or read-out current, no information will be written in, nor

will it be extracted. On the other hand, since the writein current through the selected core becomes irregular and the amplitudes in the positive and negative directions are different, as shown by the waveform 3, exceeding the amplitude of write-in current 1, the Write-in operation will be performed. Although an example has been described in FIG. 4 referring to a case in Which the aforementioned relationship will hold even if the ratio of may deviate fromthe value of 1:0.4 to a certain extent. A certain amount of allowance will also be permitted for the phase difference of It is also to be noted that the invention is not limited to cosine functions; conversions to other functions such as sine are easily accomplished and would provide equivalent results.

To recapitulate, this system offers an address selection method for magnetic-core matrix memory apparatus, which dispenses with both the switching-over operation for a current of frequency 2 of comparatively large power and the rigorous characteristics of magnetic cores.

While 1 have described above the principles of my invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of my invention as set forth in the objects thereof and in the accompanying claims.

What is claimed is:

1. An address selection system for a magnetic core memory apparatus having a plurality of magnetic cores arranged in columns and rows comprising a row wire serially coupled to each core of a row, a column wire serially coupled to each core of a column, a further wire serially coupled to all of the cores of the matrix, means for feeding an alternating current of formula to a row wire, means for feeding an alternating current of formula I cos(te15 to a column wire, means for feeding an alternating current of formula :KI cos (2wt) to said further Wire wherein KEA and I the current necessary to saturate a core and W=21rf, whereby the core selected by the occurrence of all three of said currents may be urged to one magnetic state.

2. An address selection system for a magnetic core memory apparatus, as defined in claim 1, in which the means for feeding alternating current to the further wire comprises a parametron switch.

3. An address selection system for a magnetic core memory apparatus having a plurality of magnetic cores arranged in columns and rows comprising a row Wire serially coupled to each core of a row, a column wire serially coupled to each core of a column, a further wire serially coupled to all of the cores of the matrix, means for feeding an alternating current of formula I cos (wz+X) to each row wire, means for feeding an alternating current of formula 1 cos (wt-X) to each column wire, and means connected to said further wire for recognizing and amplifying the phase of the frequency output thereon, wherein I the current necessary to saturate a core and 4. An address selection system as claimed in claim 3 in which said last mentioned means comprises a parametron and means for deriving from said parametron a current of :1, cos (2wt).

References Cited in the tile of this patent UNITED STATES PATENTS 2,845,61l Williams July 22, 1958 2,928,003 Hidetosi Takahasi et al. Mar. 8, 1960 2,928,053 Zen Eti Kiyasu et al Mar. 8, 1960 2,946,045 Eiichi Goto July 19, 1960 2,948,818 Eiichi Goto Aug. 9, 1960 2,958,074 Kilburn et a1 Oct. 25, 1960 OTHER REFERENCES A Radio Frequency Nondestructive Readout for Magnetic Core Memories by B. Widrow. Transactions of the I.R.E., December 1954, pp. 12-15. 

1. AN ADDRESS SELECTION SYSTEM FOR A MAGNETIC CORES MEMORY APPARATUS HAVING A PLURALITY OF MAGNETIC CORES ARRANGED IN COLUMNS AND ROWS COMPRISING A ROW WIRE SERIALLY COUPLED TO EACH CORE OF A ROW, A COLUMN WIRE SERIALLY COUPLED TO EACH CORE OF A COLUMN, A FURTHER WIRE SERIALLY COUPLED TO ALL OF THE CORES OF THE MATRIX, MEANS FOR FEEDING AN ALTERNATING CURRENT OF FORMULA 